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PRODID:-//Microsoft Corporation//Outlook MIMEDIR//EN
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DTSTART:20111116T011500Z
DTEND:20111116T030000Z
LOCATION:WSCC North Galleria 2nd/3rd Floors
DESCRIPTION;ENCODING=QUOTED-PRINTABLE:ABSTRACT: Increased programmability, high arithmetic precision and massive amounts of parallelism have propelled GPUs to the forefront of high-performance computing. However, achieving a high fraction of peak on GPUs still remains a challenge.=0A          A critical aspect of GPU performance is the careful placement and orchestration of application data in different memory subspaces including registers, global, local, constant, shared and texture memory. This research focuses on the register subspace. =0A          The poster proposes a framework that allows us to (1) estimate register pressure of CUDA programs at the source-level, (2) analyze its impact on application performance and (3) apply this knowledge to guide high-level code transformations, such as thread coarsening and thinning, loop fusion and unroll-and-jam, for increased effectiveness. Preliminary experiments reveal interesting non-linear relationships between register pressure and occupancy on several CUDA kernels.
SUMMARY:Register Pressure Aware Code Transformations On GPU
PRIORITY:3
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