SC is the International Conference for
High Performance Computing, Networking,
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SCHEDULE: NOV 12-18, 2011

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High-Performance Lattice QCD for Multi-core Based Parallel Systems Using a Cache-Friendly Hybrid Threaded-MPI Approach



TIME: 1:30PM - 2:00PM

AUTHOR(S):Mikhail Smelyanskiy, Karthikeyan Vaidyanathan, Jee Choi, Balint Joo, Jatin Chhugani, Michael A. Clark, Pradeep Dubey


QCD is a computationally challenging problem that solves the discretized Dirac equation. Its key operation is a matrix-vector product (Dslash operator). We have developed a novel multi-core architecture-friendly Wilson-Dslash operator which delivers 75Gflops (single-precision) on Intel Xeon processor, achieving 60% computational efficiency for datasets that fit in the last-level cache. For larger datasets, performance drops to 50Gflops. Our performance is 2-3x higher than a well-known Chroma implementation when running on the same hardware platform. The novel implementation of QCD reported is based on recently published 3.5D spatial and 4.5D temporal tiling schemes. Both schemes significantly reduce QCD external memory bandwidth requirements, delivering a more compute-bound implementation. The performance advantage of our schemes will become more significant as the gap between compute and memory bandwidth continues to grow. We further demonstrate very good cluster-level scalability achieving 4Tflops using 128 nodes for 32x32x32×256 lattice and 3Tflops for the full CG solver.

Chair/Author Details:

Mikhail Smelyanskiy - Intel Corporation

Karthikeyan Vaidyanathan - Intel Corporation

Jee Choi - Georgia Tech

Balint Joo - Jefferson Lab

Jatin Chhugani - Intel Corporation

Michael A. Clark - Harvard-Smithsonian Center for Astrophysics

Pradeep Dubey - Intel Corporation

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The full paper can be found in the ACM Digital Library

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