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Register Pressure Aware Code Transformations On GPU
SESSION: Research Poster Reception
EVENT TYPE: ACM Student Research Competition Poster, Poster, Electronic Poster
TIME: 5:15PM - 7:00PM
SESSION CHAIR: Bernd Mohr
AUTHOR(S):Swapneela Unkule, Apan Qasem
ROOM:WSCC North Galleria 2nd/3rd Floors
ABSTRACT: Increased programmability, high arithmetic precision and massive amounts of parallelism have propelled GPUs to the forefront of high-performance computing. However, achieving a high fraction of peak on GPUs still remains a challenge.
A critical aspect of GPU performance is the careful placement and orchestration of application data in different memory subspaces including registers, global, local, constant, shared and texture memory. This research focuses on the register subspace.
The poster proposes a framework that allows us to (1) estimate register pressure of CUDA programs at the source-level, (2) analyze its impact on application performance and (3) apply this knowledge to guide high-level code transformations, such as thread coarsening and thinning, loop fusion and unroll-and-jam, for increased effectiveness. Preliminary experiments reveal interesting non-linear relationships between register pressure and occupancy on several CUDA kernels.
Bernd Mohr (Chair) - Juelich Supercomputing Centre