SC is the International Conference for
High Performance Computing, Networking,
Storage and Analysis



SCHEDULE: NOV 12-18, 2011

When viewing the Technical Program schedule, on the far righthand side is a column labeled "PLANNER." Use this planner to build your own schedule. Once you select an event and want to add it to your personal schedule, just click on the calendar icon of your choice (outlook calendar, ical calendar or google calendar) and that event will be stored there. As you select events in this manner, you will have your own schedule to guide you through the week.

You can also create your personal schedule on the SC11 app (Boopsie) on your smartphone. Simply select a session you want to attend and "add" it to your plan. Continue in this manner until you have created your own personal schedule. All your events will appear under "My Event Planner" on your smartphone.

Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multi-Core Simulation

SESSION: Multicore Architectural Tools

EVENT TYPE: Paper

TIME: 3:30PM - 4:00PM

AUTHOR(S):Trevor E. Carlson, Wim Heirman, Lieven Eeckhout

ROOM:TCC 305

ABSTRACT:
Two major trends in high-performance computing, namely, larger numbers of cores and the growing size of on-chip cache memory, are creating significant challenges for evaluating the design space of future processor architectures. Fast and scalable simulations are therefore needed to sufficiently explore large multi-core systems within a limited simulation time budget. By bringing together accurate high abstraction analytical models with fast parallel simulation, architects can trade off accuracy with simulation speed to run applications longer, covering a larger portion of the hardware design space. Interval simulation provides this balance, while still providing the detail necessary to observe core-uncore interactions across the entire system. Validations against real hardware show average absolute errors within 25% for a variety of multi-threaded workloads; more than twice as accurate on average than one-IPC simulation. Further, we demonstrate scalable simulation speed of up to 2.0 MIPS when simulating a 16-core system on an 8-core SMP machine.

Chair/Author Details:

Trevor E. Carlson - Ghent University

Wim Heirman - Ghent University

Lieven Eeckhout - Ghent University

Add to iCal  Click here to download .ics calendar file

Add to Outlook  Click here to download .vcs calendar file

Add to Google Calendarss  Click here to add event to your Google Calendar

The full paper can be found in the ACM Digital Library

   Sponsors    ACM    IEEE