SC is the International Conference for
High Performance Computing, Networking,
Storage and Analysis

SCHEDULE: NOV 12-18, 2011

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System Implications of Memory Reliability in Exascale Computing

SESSION: Reliability


TIME: 2:30PM - 3:00PM

AUTHOR(S):Sheng Li, Ke Chen, Ming-Yu Hsieh, Naveen Muralimanohar, Chad Kersey, Jay B. Brockman, Arun F. Rodrigues, Norman P. Jouppi


Resiliency will be one of the toughest challenges in future exascale systems. Memory errors contribute more than 40% of the total hardware-related failures and are projected to increase in future exascale systems. Error correction code (ECC) and checkpointing are two effective approaches to fault tolerance. While there are numerous studies on ECC or checkpointing in isolation, this is the first paper to investigate the combined effect of both on overall system performance and power. We study the impact of various ECC schemes (SECDEC, BCH, and chipkill) in conjunction with checkpointing on future exascale systems. Our simulation results show that while chipkill is better for computation-intensive applications, BCH has advantage in system energy-delay product (EDP) for memory-intensive applications. We also propose to use BCH in tagged memory systems with commodity DRAMs where chipkill is impractical. The proposed architecture achieves 2X better system EDP and reliability than conventional tagged memory systems.

Chair/Author Details:

Sheng Li - Hewlett-Packard Labs

Ke Chen - University of Notre Dame

Ming-Yu Hsieh - Sandia National Laboratories

Naveen Muralimanohar - Hewlett-Packard Labs

Chad Kersey - Georgia Institute of Technology

Jay B. Brockman - University of Notre Dame

Arun F. Rodrigues - Sandia National Laboratories

Norman P. Jouppi - Hewlett-Packard Labs

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The full paper can be found in the ACM Digital Library

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